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document no. e1250e20 (ver. 2.0) date published march 2008 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2007-2008 preliminary data sheet 4gb registered ddr3 sdram dimm ebj41re4bafa (512m words 72 bits, 2 ranks) specifications ? density: 4gb ? organization ? 512m words 72 bits, 2 ranks ? mounting 36 pieces of 1g bits ddr3 sdram sealed in fbga ? package: 240-pin socket type dual in line memory module (dimm) ? pcb height: 30.5mm (max.) ? lead pitch: 1.0mm ? lead-free (rohs compliant) ? power supply: vdd = 1.5v 0.075v ? data rate: 1333mbps/1066mbps/800mbps (max.) ? eight internal banks for concurrent operation (components) ? interface: sstl_15 ? burst lengths (bl): 8 and 4 with burst chop (bc) ? /cas latency (cl): 5, 6, 7, 8, 9 ? /cas write latency (cwl): 5, 6, 7 ? precharge: auto precharge option for each burst access ? refresh: auto-refresh, self-refresh ? refresh cycles ? average refresh period 7.8 s at 0 c tc + 85 c 3.9 s at + 85 c < tc + 95 c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architecture; two data transfers per clock cycle ? the high-speed data transfer is realized by the 8 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? posted /cas by programmable additive latency for better command and data bus efficiency ? on-die-termination (odt) for better signal quality ? synchronous odt ? dynamic odt ? asynchronous odt ? multi purpose register (mpr) for temperature read out ? zq calibration for dq drive and odt ? programmable partial array self-refresh (pasr) ? /reset pin for power-up sequence and reset function ? srt range: ? normal/extended ? auto/manual self-refresh ? programmable output driver impedance control ? 1 piece of registering clock driver and 1 piece of serial eeprom (256 bytes eeprom) for presence detect (pd) ? class b temperature sensor functionality with eeprom
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 2 ordering information part number data rate mbps(max.) component jedec speed bin* 1 (cl-trcd-trp) package contact pad mounted devices EBJ41RE4BAFA-DG-E 1333 ddr3-1333g (8-8-8) 240-pin dimm (lead-free) gold edj1104base-dg-e ebj41re4bafa-dj-e ddr3-1333h (9-9-9) edj1104base-dg-e edj1104base-dj-e ebj41re4bafa-ae-e 1066 ddr3-1066f (7-7-7) edj1104base-dg-e edj1104base-dj-e edj1104base-ae-e ebj41re4bafa-ag-e ddr3-1066g (8-8-8) edj1104base-dg-e edj1104base-dj-e edj1104base-ae-e edj1104base-ag-e ebj41re4bafa-8a-e 800 ddr3-800d (5-5-5) edj1104base-dg-e edj1104base-dj-e edj1104base-ae-e edj1104base-ag-e edj1104base-8a-e ebj41re4bafa-8c-e ddr3-800e (6-6-6) edj1104base-dg-e edj1104base-dj-e edj1104base-ae-e edj1104base-ag-e edj1104base-8a-e edj1104base-8c-e note: 1. module /cas latency = component cl + 1.
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 3 pin configurations 1 pin front side back side 48 pin 49 pin 120 pin 121 pin 168 pin 169 pin 240 pin pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vrefdq 61 a2 121 vss 181 a1 2 vss 62 vdd 122 dq4 182 vdd 3 dq0 63 nc 123 dq5 183 vdd 4 dq1 64 nc 124 vss 184 ck0 5 vss 65 vdd 125 dqs9 185 /ck0 6 /dqs0 66 vdd 126 /dqs9 186 vdd 7 dqs0 67 vrefca 127 vss 187 /event 8 vss 68 par_in 128 dq6 188 a0 9 dq2 69 vdd 129 dq7 189 vdd 10 dq3 70 a10(ap) 130 vss 190 ba1 11 vss 71 ba0 131 dq12 191 vdd 12 dq8 72 vdd 132 dq13 192 /ras 13 dq9 73 /we 133 vss 193 /cs0 14 vss 74 /cas 134 dqs10 194 vdd 15 /dqs1 75 vdd 135 /dqs10 195 odt0 16 dqs1 76 /cs1 136 vss 196 a13 17 vss 77 odt1 137 dq14 197 vdd 18 dq10 78 vdd 138 dq15 198 nc 19 dq11 79 nc 139 vss 199 vss 20 vss 80 vss 140 dq20 200 dq36 21 dq16 81 dq32 141 dq21 201 dq37 22 dq17 82 dq33 142 vss 202 vss 23 vss 83 vss 143 dqs11 203 dqs13 24 /dqs2 84 /dqs4 144 /dqs11 204 /dqs13 25 dqs2 85 dqs4 145 vss 205 vss 26 vss 86 vss 146 dq22 206 dq38 27 dq18 87 dq34 147 dq23 207 dq39 28 dq19 88 dq35 148 vss 208 vss 29 vss 89 vss 149 dq28 209 dq44 30 dq24 90 dq40 150 dq29 210 dq45 31 dq25 91 dq41 151 vss 211 vss 32 vss 92 vss 152 dqs12 212 dqs14 33 /dqs3 93 /dqs5 153 /dqs12 213 /dqs14 34 dqs3 94 dqs5 154 vss 214 vss 35 vss 95 vss 155 dq30 215 dq46 36 dq26 96 dq42 156 dq31 216 dq47
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 4 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 37 dq27 97 dq43 157 vss 217 vss 38 vss 98 vss 158 cb4 218 dq52 39 cb0 99 dq48 159 cb5 219 dq53 40 cb1 100 dq49 160 vss 220 vss 41 vss 101 vss 161 dqs17 221 dqs15 42 /dqs8 102 /dqs6 162 /dqs17 222 /dqs15 43 dqs8 103 dqs6 163 vss 223 vss 44 vss 104 vss 164 cb6 224 dq54 45 cb2 105 dq50 165 cb7 225 dq55 46 cb3 106 dq51 166 vss 226 vss 47 vss 107 vss 167 nc 227 dq60 48 vtt 108 dq56 168 /reset 228 dq61 49 vtt 109 dq57 169 cke1 229 vss 50 cke0 110 vss 170 vdd 230 dqs16 51 vdd 111 /dqs7 171 a15 231 /dqs16 52 ba2 112 dqs7 172 a14 232 vss 53 /err_out 113 vss 173 vdd 233 dq62 54 vdd 114 dq58 174 a12 234 dq63 55 a11 115 dq59 175 a9 235 vss 56 a7 116 vss 176 vdd 236 vddspd 57 vdd 117 sa0 177 a8 237 sa1 58 a5 118 scl 178 a6 238 sda 59 a4 119 sa2 179 vdd 239 vss 60 vdd 120 vtt 180 a3 240 vtt
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 5 pin description pin name function a0 to a15 address input row address a0 to a13 column address a0 to a9, a11 a10 (ap) auto precharge a12 (/bc) burst chop ba0, ba1, ba2 bank select address dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) /ras row address strobe command /cas column address strobe command /we write enable /cs0, /cs1 chip select cke0, cke1 clock enable ck0 clock input /ck0 differential clock input dqs0 to dqs17, /dqs0 to /dqs17 input and output data strobe scl clock input for serial pd sda data input/output for serial pd sa0, sa1, sa2 serial address input vdd power for internal circuit vddspd power for serial eeprom vrefca reference voltage for ca vrefdq reference voltage for dq vss ground vtt termination voltage /reset set dram to known state odt0, odt1 odt control par_in parity bit for the address and control bus /err_out parity error found on the address and control bus /event reserved for optional hardware temperature sensing nc no connection
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 6 serial pd matrix byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of serial pd bytes written/spd device size/crc coverage 1 0 0 1 0 0 1 0 92h crc 0-116/256/176 1 spd revision 0 0 0 0 0 1 0 1 05h revision 0.5 2 key byte/dram device type 0 0 0 0 1 0 1 1 0bh ddr3 sdram 3 key byte/module type 0 0 0 0 0 0 0 1 01h registered 4 sdram density and banks 0 0 0 0 0 0 1 0 02h 1g bits, 8 banks 5 sdram addressing 0 0 0 1 0 0 1 0 12h 14 rows, 11 columns 6 reserved 0 0 0 0 0 0 0 0 00h ? 7 module organization 0 0 0 0 1 0 0 0 08h 2 ranks/ 4 bits 8 module memory bus width 0 0 0 0 1 0 1 1 0bh 72 bits / ecc 9 fine timebase (ftb) dividend/divi sor 0 1 0 1 0 0 1 0 52h 5 / 2 10 medium timebase (mtb) di vidend 0 0 0 0 0 0 0 1 01h 1 11 medium timebase (mtb) divi sor 0 0 0 0 1 0 0 0 08h 8 12 sdram minimum cycle time (tck (min.)) -dg, -dj 0 0 0 0 1 1 0 0 0ch 1.5ns -ae, -ag 0 0 0 0 1 1 1 1 0fh 1.875ns -8a, -8c 0 0 0 1 0 1 0 0 14h 2.5ns 13 reserved 0 0 0 0 0 0 0 0 00h ? 14 sdram /cas latencies supported, lsb -dg 0 0 1 1 1 1 1 0 3eh cl = 5, 6, 7, 8, 9 -dj 0 0 1 1 0 1 0 0 34h cl = 6, 8, 9 -ae 0 0 0 1 1 1 0 0 1ch cl = 6, 7, 8 -ag 0 0 0 1 0 1 0 0 14h cl = 6, 8 -8a 0 0 0 0 0 1 1 0 06h cl = 5, 6 -8c 0 0 0 0 0 1 0 0 04h cl = 6 15 sdram /cas latencies supported, msb 0 0 0 0 0 0 0 0 00h ? 16 sdram minimum /cas latencies time (taa (min.)) -dg 0 1 1 0 0 0 0 0 60h 12ns -dj 0 1 1 0 1 1 0 0 6ch 13.5ns -ae 0 1 1 0 1 0 0 1 69h 13.125ns -ag 0 1 1 1 1 0 0 0 78h 15ns -8a 0 1 1 0 0 1 0 0 64h 12.5ns -8c 0 1 1 1 1 0 0 0 78h 15ns 17 sdram write recovery time (twr) 0 1 1 1 1 0 0 0 78h 15ns 18 sdram minimum /ras to /cas delay (trcd) -dg 0 1 1 0 0 0 0 0 60h 12ns -dj 0 1 1 0 1 1 0 0 6ch 13.5ns -ae 0 1 1 0 1 0 0 1 69h 13.125ns -ag 0 1 1 1 1 0 0 0 78h 15ns -8a 0 1 1 0 0 1 0 0 64h 12.5ns -8c 0 1 1 1 1 0 0 0 78h 15ns
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 19 sdram minimum row active to row active delay (trrd) -dg, -dj 0 0 1 1 0 0 0 0 30h 6ns -ae, -ag 0 0 1 1 1 1 0 0 3ch 7.5ns -8a, -8c 0 1 0 1 0 0 0 0 50h 10ns 20 sdram minimum row precharge time (trp) -dg 0 1 1 0 0 0 0 0 60h 12ns -dj 0 1 1 0 1 1 0 0 6ch 13.5ns -ae 0 1 1 0 1 0 0 1 69h 13.125ns -ag 0 1 1 1 1 0 0 0 78h 15ns -8a 0 1 1 0 0 1 0 0 64h 12.5ns -8c 0 1 1 1 1 0 0 0 78h 15ns 21 sdram upper nibbles for tras and trc 0 0 0 1 0 0 0 1 11h 22 sdram minimum active to precharge time (tras), lsb -dg, -dj 0 0 1 0 0 0 0 0 20h 36ns -ae, -ag, -8a, -8c 0 0 1 0 1 1 0 0 2ch 37.5ns 23 sdram minimum active to active /auto- refresh time (trc), lsb -dg 1 0 0 0 0 0 0 0 80h 48ns -dj 1 0 0 0 1 1 0 0 8ch 49.5ns -ae 1 0 0 1 0 1 0 1 95h 50.625ns -ag 1 0 1 0 0 1 0 0 a4h 52.5ns -8a 1 0 0 1 0 0 0 0 90h 50ns -8c 1 0 1 0 0 1 0 0 a4h 52.5ns 24 sdram minimum refresh recovery time delay (trfc), lsb 0 1 1 1 0 0 0 0 70h 110ns 25 sdram minimum refresh recovery time delay (trfc), msb 0 0 0 0 0 0 1 1 03h 110ns 26 sdram minimum internal write to read command delay (twtr) 0 0 1 1 1 1 0 0 3ch 7.5ns 27 sdram minimum internal read to precharge command delay (trtp) 0 0 1 1 1 1 0 0 3ch 7.5ns 28 upper nibble for tfaw -dg, -dj 0 0 0 0 0 0 0 0 00h -ae, -ag, -8a, -8c 0 0 0 0 0 0 0 1 01h 29 minimum four activate window delay time (tfaw) -dg, -dj 1 1 1 1 0 0 0 0 f0h 30ns -ae, -ag 0 0 1 0 1 1 0 0 2ch 37.5ns -8a, -8c 0 1 0 0 0 0 0 0 40h 40ns 30 sdram output drivers supported 1 0 0 0 0 0 1 1 83h dll-off, rzq/6, 7 31 sdram refresh options 1 0 0 0 0 0 0 0 80h pasr / 2x refresh 32 thermal sensor 1 0 0 0 0 0 0 0 80h incorporated 33 sdram type 0 0 0 0 0 0 0 0 00h standard 34 to 59 reserved 0 0 0 0 0 0 0 0 00h ? 60 module nominal height 0 0 0 1 0 0 0 0 10h 30 < height 31mm 61 module maximum thickness 0 0 0 1 0 0 0 1 11h
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 8 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 62 reference raw card used 0 0 0 0 0 1 0 0 04h raw card e 63 address mapping from edge connecter to dram 0 0 0 0 0 0 0 0 00h 0 = standard 1 = mirrored 64 heat spreader solution 0 0 0 0 0 0 0 0 00h not incorporated 65 register vender id (lsb) (inphi) 1 0 0 0 0 1 0 0 84h naming bank=5 (idt) 1 0 0 0 0 0 0 0 80h naming bank=1 (ti) 1 0 0 0 0 0 0 0 80h naming bank=1 66 register vender id (msb) (inphi) 1 0 1 1 0 0 1 1 b3h actual id (idt) 1 0 1 1 0 0 1 1 b3h (ti) 1 0 0 1 0 1 1 1 97h 67 register revision (inphi) 0 0 0 0 0 0 0 1 01h rev.2 (idt) 0 1 0 1 0 1 0 0 54h rev.5 (ti) 0 0 0 1 0 1 1 0 16h rev. 2.1 68 register type 0 0 0 0 0 0 0 0 00h sste32882 69 register control word function (rc0, 1) (inphi) 0 0 0 0 0 0 1 0 02h (idt) 0 0 0 0 0 0 0 0 00h (ti) 0 0 0 0 0 0 1 0 02h 70 register control word function (rc2, 3) (inphi) 0 1 0 1 0 0 0 0 50h (idt) 0 1 0 1 0 0 0 0 50h (ti) 1 0 1 0 0 0 0 0 a0h 71 register control word function (rc4, 5) (inphi) 0 1 0 1 0 1 0 1 55h (idt) 0 1 0 1 0 1 0 1 55h (ti) 1 0 1 0 0 1 0 1 a5h 72 register control word function (rc6, 7) (inphi) 1 0 0 0 0 0 0 0 80h (idt) 0 0 0 0 0 0 0 1 01h (ti) 0 0 0 0 0 0 0 0 00h 73 register control word function (rc8, 9) (inphi) 0 0 0 0 0 0 0 0 00h (idt) 1 0 0 0 0 0 0 0 80h (ti) 1 0 0 1 0 0 0 0 90h 74 register control word function (rc10, 11) (inphi) 0 0 0 0 0 0 0 0 00h (idt) 0 0 0 0 0 0 0 0 00h (ti) 0 0 0 0 0 0 0 0 00h 75 register control word function (rc12, 13) (inphi) 1 0 1 0 0 0 0 0 a0h (idt) 0 0 0 0 0 0 0 0 00h (ti) 0 0 0 0 0 0 0 0 00h
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 9 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 76 register control word function (rc14, 15) (inphi) 0 0 0 0 0 0 1 0 02h (idt) 0 0 0 0 0 0 0 0 00h (ti) 0 0 0 0 0 0 0 0 00h 77 to 116 module specific section 0 0 0 0 0 0 0 0 00h ? 117 module id: manufacturer?s jedec id code, lsb 0 0 0 0 0 0 1 0 02h elpida memory 118 module id: manufacturer?s jedec id code, msb 1 1 1 1 1 1 1 0 feh elpida memory 119 module id: manufacturing location 120 module id: manufacturing date year code (bcd) 121 module id: manufacturing date week code (bcd) 122 to 125 module id: module serial number 126 cyclical redundancy code (crc) -dg (inphi) 0 1 0 0 0 0 1 0 42h (idt) 1 1 0 1 1 0 0 0 d8h (ti) 1 1 1 0 0 0 1 0 e2h -dj (inphi) 1 0 1 1 0 1 0 1 b5h (idt) 0 0 1 0 1 1 1 1 2fh (ti) 0 0 0 1 0 1 0 1 15h -ae (inphi) 0 1 1 0 0 1 1 1 67h (idt) 1 1 1 1 1 1 0 1 fdh (ti) 1 1 0 0 0 1 1 1 c7h -ag (inphi) 0 0 0 0 0 1 0 0 04h (idt) 1 0 0 1 1 1 1 0 9eh (ti) 1 0 1 0 0 1 0 0 a4h -8a (inphi) 1 1 1 1 0 0 0 0 f0h (idt) 0 1 1 0 1 0 1 0 6ah (ti) 0 1 0 1 0 0 0 0 50h -8c (inphi) 1 1 1 1 1 1 1 1 ffh (idt) 0 1 1 0 0 1 0 1 65h (ti) 0 1 0 1 1 1 1 1 5fh
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 10 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 127 cyclical redundancy code (crc) -dg (inphi) 0 0 1 0 1 1 0 0 2ch (idt) 0 1 0 1 0 0 1 0 52h (ti) 1 0 0 0 0 1 1 1 87h -dj (inphi) 1 0 0 0 0 1 0 0 84h (idt) 1 1 1 1 1 0 1 0 fah (ti) 0 0 1 0 1 1 1 1 2fh -ae (inphi) 1 0 1 0 0 0 1 0 a2h (idt) 1 1 0 1 1 1 0 0 dch (ti) 0 0 0 0 1 0 0 1 09h -ag (inphi) 0 1 0 1 0 1 1 1 57h (idt) 0 0 1 0 1 0 0 1 29h (ti) 1 1 1 1 1 1 0 0 fch -8a (inphi) 0 0 0 0 1 0 1 0 0ah (idt) 0 1 1 1 0 1 0 0 74h (ti) 1 0 1 0 0 0 0 1 a1h -8c (inphi) 1 1 1 1 1 0 1 1 fbh (idt) 1 0 0 0 0 1 0 1 85h (ti) 0 1 0 1 0 0 0 0 50h 128 module part number 0 1 0 0 0 1 0 1 45h e 129 module part number 0 1 0 0 0 0 1 0 42h b 130 module part number 0 1 0 0 1 0 1 0 4ah j 131 module part number 0 0 1 1 0 1 0 0 34h 4 132 module part number 0 0 1 1 0 0 0 1 31h 1 133 module part number 0 1 0 1 0 0 1 0 52h r 134 module part number 0 1 0 0 0 1 0 1 45h e 135 module part number 0 0 1 1 0 1 0 0 34h 4 136 module part number 0 1 0 0 0 0 1 0 42h b 137 module part number 0 1 0 0 0 0 0 1 41h a 138 module part number 0 1 0 0 0 1 1 0 46h f 139 module part number 0 1 0 0 0 0 0 1 41h a 140 module part number 0 0 1 0 1 1 0 1 2dh ? 141 module part number -dg, -dj 0 1 0 0 0 1 0 0 44h d -ae, -ag 0 1 0 0 0 0 0 1 41h a -8a, -8c 0 0 1 1 1 0 0 0 38h 8
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 11 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 142 module part number -dg, -ag 0 1 0 0 0 1 1 1 47h g -dj 0 1 0 0 1 0 1 0 4ah j -8c 0 1 0 0 0 0 1 1 43h c -ae 0 1 0 0 0 1 0 1 45h e -8a 0 1 0 0 0 0 0 1 41h a 143 module part number 0 0 1 0 1 1 0 1 2dh ? 144 module part number 0 1 0 0 0 1 0 1 45h e 145 module part number 0 0 1 0 0 0 0 0 20h (space) 146 module revision code 0 0 1 1 0 0 0 0 30h initial 147 module revision code 0 0 1 0 0 0 0 0 20h (space) 148 sdram manufacturer?s jedec id code, lsb 149 sdram manufacturer?s jedec id code, msb 150 to 175 manufacturer's specific data 0 0 0 0 0 0 0 0 00h 176 to 255 open for customer use
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 12 block diagram vtt dqs14 /dqs14 4 dq24 to dq27 dqs1 /dqs1 4 dq8 to dq11 dqs9 /dqs9 4 dq4 to dq7 dqs2 /dqs2 4 4 4 4 4 dq16 to dq19 dqs3 /dqs3 dqs16 /dqs16 dq60 to dq63 dqs7 /dqs7 dq56 to dq59 dqs4 /dqs4 dq32 to dq35 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 d22 d34 d25 d3 d2 d1 d9 d21 d20 d19 d27 zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck rs1 rs1 rs1 rs1 rs3 rs3 rs3 rs3 rs3 vtt rs3 rs3 rs3 vtt rs3 rs3 rs3 rs3 rs3 rs4 rs4 rs4 rs4 vtt rs3 rs3 rs3 rs1 rs1 4 dqs8 /dqs8 cb0 to cb3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 d8 d26 zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 dm dm dm dm dm dm dm vss vss vss dm vss vss dm dm rs1 vtt dq28 to dq31 dqs10 /dqs10 dq12 to dq15 dqs0 /dqs0 dq0 to dq3 dqs11 /dqs11 4 4 4 4 dq20 to dq23 dqs12 /dqs12 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 pck0_a pck1_a rcke0_a rcke1_a rodt0_a rodt1_a /pck0_a /pck1_a /rcs0_a /rcs1_a [address, ba]_a rcommand_a d12 d11 d10 d0 d30 d29 d28 d18 zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck rs1 rs3 rs3 rs3 rs3 rs3 vtt rs3 rs3 rs3 rs1 rs1 4 dqs17 /dqs17 cb4 to cb7 dqs /dqs dq0 to dq3 d17 zq /cs address ba command odt cke ck /ck rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 dm dm dm dm dm dm dm vss vss vss dm vss vss dm rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 /dqs dq0 to dq3 d32 zq /cs address ba command odt cke ck /ck d16 dqs zq /dqs dm dm dq0 to dq3 /cs address ba command odt cke ck /ck dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dm dm dm dm dm dm dq0 to dq3 zq /cs address ba command odt cke ck /ck zq /cs address ba odt cke ck /ck zq /cs address ba command odt cke ck /ck d14 d4 d7 command dqs dq44 to dq47 vss vss vss vss dqs13 /dqs13 4 4 4 4 dqs15 /dqs15 dq52 to dq55 dqs6 /dqs6 dq48 to dq51 dqs5 /dqs5 dq40 to dq43 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 d23 d33 d24 zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck zq /cs address ba command odt cke ck /ck rs1 rs1 rs1 vtt rs3 rs3 rs3 rs3 rs3 vtt rs3 rs3 rs3 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 rs1 /dqs dq0 to dq3 d31 zq /cs address ba command odt cke ck /ck d15 dqs zq /dqs dm dm dq0 to dq3 /cs address ba command odt cke ck /ck dqs /dqs dq0 to dq3 dqs /dqs dq0 to dq3 dqs /dqs dm dm dm dm dm dm dq0 to dq3 zq /cs address ba command odt cke ck /ck zq /cs address ba odt cke ck /ck zq /cs address ba command odt cke ck /ck d13 d5 d6 command dqs dq36 to dq39 vss vss vss vss dqs /dqs dq0 to dq3 d35 zq /cs address ba command odt cke ck /ck dm 3 17 pck0_a pck1_a rcke0_a rcke1_a rodt0_a rodt1_a /pck0_a /pck1_a /rcs0_a /rcs1_a [address, ba]_a rcommand_a 3 17 pck0_b pck1_b rcke1_b rcke0_b rodt1_b rodt0_b /pck0_b /pck1_b /rcs1_b /rcs0_b [address, ba]_b rcommand_b pck0_b pck1_b rcke1_b rcke0_b rodt1_b rodt0_b /pck0_b /pck1_b /rcs1_b /rcs0_b [address, ba]_b rcommand_b 3 17 3 17 rs4 rs4 rs4 rs4 block diagram (1)
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 13 notes : 1. dq wiring may be changed. 2. see the wiring diagrams for all resistors associated with the command, address and control bus. * d0 to d35: 1g bits ddr3 sdram address, ba: a0 to a15, ba0 to ba2 command: /ras, /cas, /we u1: 256 bytes eeprom rs1: 15 rs2: 22 rs3: 36 rs4: 120 register: sste32882 r s2 r s2 r s2 r s2 r s2 r s2 r s2 r s2 r s2 /cs0* 2 /cs1* 2 ba address command cke0 cke1 odt0 odt1 /rcs0_a -> /cs0: sdrams d0 to d3, d8 to d12, d17 /rcs0_b -> /cs0: sdrams d22 to d25, d31 to d34 /rcs1_a -> /cs1: sdrams d18 to d21, d26 to d30, d35 /rcs1_b -> /cs1: sdrams d4 to d7, d13 to d16 r e g i s t e r / p l l /reset /reset: sdrams d0 to d35 /reset ck0 r s2 rba_a -> ba0 to ba2: sdrams d0 to d3, d8 to d12, d17 to d21, d26 to d30, d35 rba_b -> ba0 to ba2: sdrams d4 to d7, d13 to d16, d22 to d25, d31 to d34 raddress_a -> a0 to a13: sdrams d0 to d3, d8 to d12, d17 to d21, d26 to d30, d35 raddress_b -> a0 to a13: sdrams d4 to d7, d13 to d16, d22 to d25, d31 to d34 rcommand_a -> /ras, /cas, /we: sdrams d0 to d3, d8 to d12, d17 to d21, d26 to d30, d35 rcommand_b -> /ras, /cas, /we: sdrams d4 to d7, d13 to d16, d22 to d25, d31 to d34 rcke0_a -> cke: sdrams d0 to d3, d8 to d12, d17 rcke0_b -> cke: sdrams d22 to d25, d31 to d34 rodt0_a -> odt: sdrams d0 to d3, d8 to d12, d17 rodt0_b -> odt: sdrams d22 to d25, d31 to d34 rcke1_a -> cke: sdrams d18 to d21, d26 to d30, d35 rcke1_b -> cke: sdrams d4 to d7, d13 to d16 rodt1_a -> odt: sdrams d18 to d21, d26 to d30, d35 rodt1_b -> odt: sdrams d4 to d7, d13 to d16 pck0_a -> ck: sdrams d0 to d3, d8 to d12, d17 pck0_b -> ck: sdrams d4 to d7, d13 to d16 pck1_a -> ck: sdrams d18 to d21, d26 to d30, d35 pck1_b -> ck: sdrams d22 to d25, d31 to d34 /ck0 par_in /err_out /pck0_a -> /ck: sdrams d0 to d3, d8 to d12, d17 /pck0_b -> /ck: sdrams d4 to d7, d13 to d16 /pck1_a -> /ck: sdrams d18 to d21, d26 to d30, d35 /pck1_b -> /ck: sdrams d22 to d25, d31 to d34 120 a2 serial pd sda a0 a1 /event /event scl sa0 sa1 sa2 sda scl u1 vddspd spd vrefdq sdrams (d0 to d35) vtt vrefca sdrams (d0 to d35) vdd sdrams (d0 to d35) vss sdrams (d0 to d35), spd d1 d2 d3 d4 register d5 d6 d7 d0 d9 d10 d11 d8 d17 d12 d13 d14 d15 d16 address, command and control line vtt vtt vtt vtt vtt vtt vtt vtt d28 d29 d30 d18 d35 d27 d19 d20 d26 d21 d22 d25 d32 d34 d23 d24 d31 d33 block diagram (2)
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 14 electrical specifications ? all voltages are referenced to vss (gnd). absolute maximum ratings parameter symbol value unit notes power supply voltage vdd ? 0.4 to +1.975 v 1, 3, 4 input voltage vin ? 0.4 to +1.975 v 1, 4 output voltage vout ? 0.4 to +1.975 v 1, 4 reference voltage vrefca ? 0.4 to 0.6 vdd v 3, 4 reference voltage for dq vrefdq ? 0.4 to 0.6 vddq v 3, 4 storage temperature tstg ? 55 to +100 c 1, 2, 4 power dissipation pd 18 w short circuit output current iout 50 ma 1, 4 notes: 1. stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only and functi onal operation of the devic e at these or any other conditions above those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface te mperature on the center/t op side of the dram. 3. vdd and vddq must be within 300m v of each other at all times; and vref must be not greater than 0.6 vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. 4. ddr3 sdram component specification. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this sp ecification exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature condition parameter symbol rating unit notes operating case temperature tc 0 to +95 c 1, 2, 3 notes: 1. operating tem perature is the case surface temperat ure on the center/top side of the dram. 2. the normal temperature range specifies the temperatur es where all dram specifications will be supported. during operati on, the dram case temperature must be maintained between 0c to +85c under all operating conditions. 3. some applications require operation of the dram in the exte nded temperature range between +85c and +95c case temperature. full s pecifications are guarant eed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9s. (this double refresh requirement may not apply for some devices.) b) if self-refresh operation is required in the extend ed temperature range, t hen it is mandatory to either use the manual self-r efresh mode with extended temperature range capability (mr2 bit [a6, a7] = [0, 1]) or enable the optional auto se lf-refresh mode (mr2 bit [a6, a7] = [1, 0]).
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 15 recommended dc operating conditions (tc = 0c to +85c) (ddr3 sdram component specification) parameter symbol min. typ. max. unit notes supply voltage vdd, vddq 1.425 1.5 1.575 v 1, 2 vss 0 0 0 v vddspd 3.0 3.3 3.6 v input reference voltage vrefca (dc) 0.49 vddq 0.50 vddq 0.51 vddq v 3, 4 input reference voltage for dq vrefdq (dc) 0.49 vddq 0.50 vddq 0.51 vddq v 3, 4 termination voltage vtt vddq/2 ? tbd tbd vddq/2 + tbd v notes: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than 1% vdd (for reference: approx 15 mv). 4. for reference: approx. vdd/2 15 mv.
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 16 dc characteristics 1 (tc = 0c to +85c, vdd = 1.5v 0.075v, vss = 0v) parameter symbol data rate (mbps) max. unit notes operating current (act-pre) idd0 1333 1066 800 tbd tbd tbd ma operating current (act-read-pre) idd1 1333 1066 800 tbd tbd tbd ma idd2pf 1333 1066 800 tbd tbd tbd ma fast pd exit precharge power-down standby current idd2ps 1333 1066 800 tbd tbd tbd ma slow pd exit precharge quiet standby current idd2q 1333 1066 800 tbd tbd tbd ma precharge standby current idd2n 1333 1066 800 tbd tbd tbd ma active power-down current (always fast exit) idd3p 1333 1066 800 tbd tbd tbd ma active standby current idd3n 1333 1066 800 tbd tbd tbd ma operating current (burst read operating) idd4r 1333 1066 800 tbd tbd tbd ma operating current (burst write operating) idd4w 1333 1066 800 tbd tbd tbd ma burst refresh current idd5b 1333 1066 800 tbd tbd tbd ma all bank interleave read current idd7r 1333 1066 800 tbd tbd tbd ma self-refresh current (tc = 0 c to +85 c, vdd = 1.5v 0.075v) parameter symbol max. unit notes self-refresh current normal temperature range idd6 tbd ma self-refresh current extended temperature range idd6et tbd ma auto self-refresh current idd6tc tbd ma
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 17 ac timing for idd test conditions for purposes of idd testing, the foll owing parameters are to be utilized. ddr3-1333 ddr3-1066 ddr3-800 parameter 8-8-8 9-9-9 7-7- 7 8-8-8 5-5-5 6-6-6 unit cl (idd) 8 9 7 8 5 6 tck tck min.(idd) 1.5 1.5 1.875 1.875 2.5 2.5 ns trcd min. (idd) 12 13.5 13.13 15 12.5 15 ns trc min. (idd) 48 49.5 50.63 52.50 50 52.5 ns tras min.(idd) 36 36 37.5 37.5 37.5 37.5 ns trp min. (idd) 12 13.5 13.13 15 12.5 15 ns tfaw (idd)- 4/ 8 30 30 37.5 37.5 40 40 ns trrd (idd)- 4/ 8 6.0 6.0 7.5 7.5 10 10 ns trfc (idd) 110 110 110 110 110 110 ns dc characteristics 2 (tc = 0c to +85c, vdd, vddq = 1.5v 0.075v) (ddr3 sdram component specification) parameter symbol value unit notes input leakage current ? ili ? tbd a vdd vin vss output leakage current ? ilo ? tbd a ddq vout vss
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 18 pin functions ck, /ck (input pin) ck and /ck are differential clock inputs. all address and c ontrol input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). /cs (input pin) all commands are masked when /cs is registered high. /cs provides for external rank selection on systems with multiple ranks. /cs is considered part of the command code. /ras, /cas, and /we (input pins) /ras, /cas and /we (along with /cs) define the command being entered. a0 to a15 (input pins) provided the row address for active commands and the co lumn address for read/write commands to select one location out of the memory array in the respective bank. (a10(ap) and a12(/bc) have additional functions, see below) the address inputs also provide t he op-code during mode register set commands. [address pins table] address (a0 to a13) row address (ra) column address (ca) notes ax0 to ax13 ay0 to ay9, a11 a10(ap) (input pin) a10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (h igh: auto-precharge; low: no auto-precharge) a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 = low) or all banks (a10 = high). if only one bank is to be prec harged, the bank is selected by bank addresses (ba). a12 (/bc) (input pin) a12 is sampled during read and write commands to determi ne if burst chop (on-the-fly) will be performed. (a12 = high: no burst chop, a12 = low: burst chopped.) ba0 to ba2 (input pins) ba0, ba1 and ba2 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determine if a mode register is to be accessed during a mrs cycle. [bank select signal table] ba0 ba1 ba2 bank 0 l l l bank 1 h l l bank 2 l h l bank 3 h h l bank 4 l l h bank 5 h l h bank 6 l h h bank 7 h h h remark: h: vih. l: vil.
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 19 cke (input pin) cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refr esh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for se lf-refresh exit. after vref has become stable during the power-on and initialization sequence, it must be maintained for proper operat ion of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck, odt and cke are disabled during power-down. input buffers, excluding cke, are disabled during self-refresh. dq and cb (input and output pins) bi-directional data bus. dqs and /dqs (input and output pin) output with read data, input with write data. edge- aligned with read data, centered in write data. the data strobe dqs is paired with differential signals /dqs to provide differential pair signaling to the system during reads and writes. odt (input pins) odt (registered high) enables termination resistance inte rnal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, /dqs, dm. the odt pin will be ignored if the mode register (mr1) is programmed to disable odt. vdd (power supply pins) 1.5v is applied. (vdd is for the internal circuit.) vddspd (power supply pin) 3.3v is applied (for serial eeprom). vss (power supply pin) ground is connected. vtt (power supply pin) termination supply. vrefdq (power supply) reference voltage for dq. vrefca (power supply) reference voltage for ca. scl (input pin) clock input for serial pd. sda (input and output pins) data input/output for serial pd. sa (input pin) serial address input. /reset (input pin) /reset is negative active signal (active low) and is referred to gnd.
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 20 par_in (input pin) parity bit for the address and control bus. /err_out (output pin) parity error found on the address and control bus. /event (output pin) reserved for optional hardware temperature sensing. detailed operation part, electrical characteristics and timing waveforms refer to the edj1104base, edj1108base, edj1116base dat asheet (e1128e). dm pins of component device fixed to vss level on the module board. dimm /c as latency = component cl + 1 for registered type.
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 21 physical outline (datum -a-) 47.00 71.00 a b 1 unit: mm 1.27 0.10 4.00 min 4.00 max 0.5 min eca-ts2-0254-01 240 121 c 2.80 min 9.50 17.30 30.50 max

component area (back) front side back side 133.35 component area (front) 120
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 22 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
ebj41re4bafa preliminary data sheet e1250e20 (ver. 2.0) 23 m01e0706 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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